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Table 1. Signal List by Ball Number (continued)
Power-
I/O Multiplexing Mode 2
Ball
Number
Signal Name
On
Reset
Value
0 (000)
1 (001)
2 (010)
3 (011)
4 (100)
5 (101)
6 (110)
7 (111)
Ref.
Supply
B10
B11
B12
B13
B14
B15
B16
B17
B18
Reserved 1
Reserved 1
SRIO_RXD0
GND SXC
SRIO_RXD1
GND SXC
SRIO_REF_CLK
Reserved 1
V DDSXC
—
—
V DDSXC
GND SXC
V DDSXC
GND SXC
V DDSXC
—
V DDSXC
B19
SRIO_RXD2/
SGMII support on SERDES is enabled by Reset Configuration Word
V DDSXC
GE1_SGMII_RX
B20
GND SXC
GND SXC
B21
SRIO_RXD3/
SGMII support on SERDES is enabled by Reset Configuration Word
V DDSXC
GE2_SGMII_RX
B22
B23
B24
B25
B26
B27
B28
GND SXC
GND SXP
MDQ27
V DDDDR
GND
V DDDDR
MDQS3
GND SXC
GND SXP
V DDDDR
V DDDDR
GND
V DDDDR
V DDDDR
C1
Reserved
1
—
C2
GE2_RX_CLK/PCI_AD29
Ethernet 2
PCI
Ethernet 2
V DDGE2
C3
V DDGE2
V DDGE2
C4
TDM7RSYN/GE2_TD2/
TDM
PCI
Ethernet 2
UTOPIA
V DDGE2
PCI_AD2/UTP_TER
C5
TDM7RCLK/GE2_RD2/
TDM
PCI
Ethernet 2
UTOPIA
V DDGE2
PCI_AD0/UTP_RVL
C6
V DDGE2
V DDGE2
C7
GE2_RD0/PCI_AD27
Ethernet 2
PCI
Ethernet 2
V DDGE2
C8
Reserved 1
—
C9
Reserved
1
—
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
Reserved 1
Reserved 1
V DDSXP
SRIO_TXD0
V DDSXP
SRIO_TXD1
GND SXC
GND RIOPLL
Reserved 1
V DDSXP
—
—
V DDSXP
V DDSXP
V DDSXP
V DDSXP
GND SXC
GND RIOPLL
—
V DDSXP
C20
SRIO_TXD2/GE1_SGMII_T
SGMII support on SERDES is enabled by Reset Configuration Word
V DDSXP
X
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
7
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